DS3231MZ+【PDF 7/20 页】IC RTC I2C 8SOIC

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Sheet目录1994

3页 4页 5页 6页 [7页]8页 9页 10页 11页

±5ppm, I2C Real-Time Clock

Maxim Integrated

DS3231M

Status Register (0Fh)

Aging Offset Register (10h)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

OSF

EN32KHZ

BSY

A2F

A1F

BIT 7

OSF: Oscillator stop flag. A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for

some period and could be used to judge the validity of the timekeeping data. This bit is set to logic 1 any time

that the oscillator stops. This bit remains at logic 1 until written to logic 0. The following are examples of

conditions that can cause the OSF bit to be set:

1) The first time power is applied.

2) The voltages present on both VCC and VBAT are insufficient to support the oscillator.

3) The EOSC bit is turned off in battery-backed mode.

4) External influences on the oscillator (i.e., noise, leakage, etc.).

BITS 6:4

Unused (0). These bits have no meaning and are fixed at 0 when read.

BIT 3

EN32KHZ: Enabled 32.768kHz output. This bit enables and disables the 32KHZ output. When set to a logic 0,

the 32KHZ output is high impedance. On initial power-up, this bit is set to a logic 1 and the 32KHZ output is

enabled and produces a 32.768kHz square wave if the oscillator is enabled.

BIT 2

BSY: Busy. This bit indicates the device is busy executing temperature conversion function. It goes to logic 1

when the conversion signal to the temperature sensor is asserted, and then it is cleared when the device has

completed the temperature conversion. See the Block Diagram for more details.

BIT 1

A2F: Alarm 2 flag. A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. If the

A2IE bit is logic 1 and the INTCN bit is set to logic 1, INT/SQW is also asserted. A2F is cleared when written to

logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.

BIT 0

A1F: Alarm 1 flag. A logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. If the

A1IE bit is logic 1 and the INTCN bit is set to logic 1, INT/SQW is also asserted. A1F is cleared when written to

logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

SIGN

DATA

The Aging Offset register takes a user-provided value to add to or subtract from the factory-trimmed value that adjusts the

accuracy of the time base. Use of the Aging Offset register is not needed to achieve the accuracy as defined in the Electrical

Characteristics tables.

The Aging Offset code is encoded in two’s complement, with bit 7 representing the SIGN bit and a valid range of ±127. One

LSB typically represents a 0.12ppm change in frequency. The change in ppm per LSB is the same over the operating tempera-

ture range. Positive offsets slow the time base and negative offsets quicken the time base.

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